1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a method of forming a self aligned silicide (salicide) having a uniform sheet resistance independent of the line width.
2. Description of the Related Art
Self aligned suicides or salicide structures are well known in the art of semiconductor processing. Typically, a refractory metal is deposited upon conductive silicon structures such as the source/drain regions of the silicon substrate or the polysilicon structures used for transistor gates and local interconnects. The refractory metal is then reacted with the silicon typically by heating the silicon wafer to a predetermined temperature. The reaction between the refractory metal and the silicon typically results in the formation of a silicide structure which has a significantly lower sheet resistance than the sheet resistance of the source/drain regions or the polysilicon structures. As a result, the contact resistance between the silicide structure and a conductive contact subsequently coupled to the source/drain region or the polysilicon structure is lowered. Therefore, substantial signal propagation delay resulting from the higher contact resistance associated with conventional source/drain and polysilicon is reduced or prevented. In a conventional salicide process, a refractory metal is deposited upon an underlying topography comprising silicon and a dielectric, such as silicon dioxide. The portion of the refractory metal in close proximity to the exposed silicon is then reacted with the silicon to form a silicide while the portions of the refractory metal in close proximity to the dielectric remain unreacted. The unreacted portions of the refractory metal can then be selectively removed resulting in a silicide that is self aligned to the underlying silicon.
Despite the lower contact resistances associated with silicide processes, it has been widely observed that the sheet resistance of conventionally formed silicide varies with the line width of the structure upon which the silicide is formed. In particular, it has been observed that sheet resistivity of silicide on narrow structures (i.e., structures having smaller lateral areas) is typically greater than the sheet resistivity of silicide formed on wide silicon structures. This variation in sheet resistivity makes process simulation and circuit simulation difficult and produces undesirable variability in the fabrication process. In a conventional two-step heat treatment process for forming a conventional titanium silicide, the variability in silicide sheet resistivity may be attributed to inadequate conversion from a first phase of the silicide (C49) to a second and lower resistivity phase of the silicide (C54). Whatever the exact cause, the observed sheet resistivities of titanium silicide in very narrow line widths (e.g., less than 0.8 microns) are unacceptably high. Attempts to increase the second temperature to enhance the conversion rate to C54 silicide typically has a detrimental effect on large area features by causing, e.g., undesirable migration of impurities. Further, attempts to address the silicide sheet resistivity variability by implanting the underlying structures with a silicon implant prior to metal deposition have been met with limited success.
Selective deposition techniques in which the metal silicide is selectively deposited upon the desired silicon features have been shown to result in improved sheet resistivity uniformity across varying line widths. Unfortunately, excessive silicon consumption can occur during the selective deposition processes, resulting in an undesirable decrease migration through the junction which can lead to catastrophic failure mechanisms. In summary, numerous techniques have been unsuccessfully explored to improve silicide sheet resistivity uniformity across varying line widths without simultaneously causing a significant reduction in reliability. It would therefore be desirable to implement a self-aligned silicide process exhibiting manufacturable and reliable integrated circuits including a substantially uniform sheet resistivity independent of the local silicide dimension.